Titanium silidde has become the most widely-used silicide in the VLSI industry for self-aligned silicide applications because of its combined characteristics of low resistivity, the ability to be self-aligned, and relatively good thermal stability. Although TiSi.sub.2 has certain advantages relative to other silicides, the fact that it is a polymorphic material presents additional problems in its use. Specifically, in typical use TiSi.sub.2 exists as either an orthorhombic base-centered phase having 12 atoms per unit cell and a resistivity of about 60-90 micro-ohm-cm (known in the industry as the C49 phase), or as a more thermodynamically-favored orthorhombic face-centered phase which has 24 atoms per unit cell and a resistivity of about 12-20 micro-ohm-cm (known as the C54 phase). When using the generally-accepted processing conditions for forming titanium silicide, the less-desirable, higher-resistivity C49 phase is formed first. In order to obtain the lower-resistivity C54 phase, a second high-temperature annealing step is required.
A typical set of processing conditions for forming C54 phase titanium silicide include: (1) pre-cleaning, (2) titanium deposition, (3) silicide formation at a temperature about 700.degree. C. or below, (4) selective etching, and (5) a phase transformation anneal at a temperature greater than about 700.degree. C. It is the phase transformation anneal that converts the dominant C49 phase to the C54 phase. The initial formation temperature is kept about 700.degree. C. or below in order to minimize over-spacer bridging. The second transformation anneal is performed after any un-reacted titanium has been selectively removed and is generally performed at temperatures of 50.degree.-200.degree. C. above the formation temperature to insure full transformation to the C54 phase for best control of sheet resistance. However, as device line-widths and silicide film thickness continue to be scaled down, the C49 to C54 transformation becomes more difficult on these narrow structures (such as narrow gate structures) due to the low C54 nucleation density.
It is generally accepted that the C49 phase forms first because of a lower surface energy than that of the C54 phase. In other words, the higher surface energy of C54 phase forms a higher energy barrier to its formation. The second transformation anneal step used in the standard process above provides the additional thermal energy necessary to both overcome the nucleation barrier associated with forming the new surface and growing the crystalline structure of the newly-forming C54 phase. In VLSI applications, if the phase transformation is inhibited or fails to occur uniformly, a degradation in circuit performance is observed. In some higher-performance circuits, the RC delay associated with a poor phase transformation is typically about 5-10 percent.
A significant limitation on the C49-to-C54 phase transformation is a phenomenon known as agglomeration. If the thermal energy used to obtain the phase transformation is excessive, then a morphological degradation of the titanium silicide results, which is commonly referred to as agglomeration. As line-widths and silicide film thickness decrease, the thermal energy required to affect the C49 -to- C54 phase transformation increases, yet the thermal energy level at which the silicide film starts to agglomerate decreases. Thus, there is an ever-shrinking process window for performing this phase transformation, making process control and uniformity more difficult to achieve.
Thus, there is a need for an improved method for forming the C54 phase titanium silicide.
One solution to this problem involves causing at least a portion of the polycrystalline silicon structure to become amorphous. This can be done by subjecting the polycrystalline silicon structure to preamorphization implant (PAI) prior to the deposition of titanium. As is described in a prior patent application assigned to Texas Instruments, Ser. No. 09/110,034 , this PAI can be accomplished by implanting either Ge or As into the polycrystalline structure so as to make it amorphous for at least 10 to 30 nm into the structure.
A problem with this method is that a fairly small percentage of the transistors formed using this method fail. More specifically, some devices will have an on-current versus off-current that is dramatically different from an average device.